Displays for ESP32-P4

What the ESP32-P4 offers for displays

The ESP32-P4 datasheet (v0.7) lists two display paths:

• MIPI DSI: 2 data lanes at up to 1.5 Gbps each, compliant with D-PHY v1.1. Input formats RGB888, RGB666, RGB565, YUV422, YUV420 and grey; output formats RGB888, RGB666 and RGB565. The panel is driven in video mode, so it needs no frame memory of its own.
• LCD_CAM: 8, 16 or 24-bit parallel output in RGB, MOTO6800 or I8080 format, on any GPIOs through the GPIO matrix.

For graphics it adds a 2D-DMA controller and a pixel-processing accelerator (PPA) that rotates (0°, 90°, 180°, 270°), scales, mirrors and alpha-blends images. Unlike the ESP32-S3, which has no MIPI DSI, the P4 can drive the MIPI DSI panels used in phones and tablets.

Lane count: check this first

Two lanes is the limit. Many 7″–10.1″ MIPI panels are designed for 4 lanes; some of them can be configured for 2, many cannot. Before you order samples, check the lane options in the panel datasheet and the init sequence the vendor supplies for 2-lane mode.

Bandwidth and frame buffers

At 60 Hz in RGB888 (24 bits per pixel), the pixel data alone is:

• 480×640: about 0.44 Gbps, frame buffer 900 KB
• 1024×600: about 0.88 Gbps, frame buffer 1,800 KB
• 720×1280: about 1.33 Gbps, frame buffer 2,700 KB (2.64 MB)
• 800×1280: about 1.47 Gbps, frame buffer 3,000 KB
• 1920×1080: about 2.99 Gbps, frame buffer about 5.9 MB

Two lanes carry up to 3 Gbps, and the panel also needs blanking periods, so 1080p at 60 Hz in RGB888 has almost no headroom; RGB565 cuts the data by a third. Every one of these frame buffers is larger than the 768 KB of on-chip L2MEM, which is why the frame buffer sits in PSRAM: ESP32-P4 chips have 16 MB (ESP32-P4NRW16X) or 32 MB (ESP32-P4NRW32X) in the package.

Bring-up checklist in ESP-IDF

The ESP-IDF MIPI DSI LCD driver sets up a display in three steps:

1. esp_lcd_new_dsi_bus() creates the bus and initialises the D-PHY: set num_data_lanes (2) and lane_bit_rate_mbps.
2. esp_lcd_new_panel_io_dbi() opens the command channel; the panel's controller driver (for example esp_lcd_new_panel_ili9881c()) sends the init sequence over it.
3. esp_lcd_new_panel_dpi() starts the video stream: dpi_clock_freq_mhz (the pixel clock), in_color_format and out_color_format, num_fbs and the video_timing porches from the panel datasheet.

Two things catch people out:

• D-PHY supply. The MIPI D-PHY needs a dedicated 2.5 V supply on VDD_MIPI_DPHY. It can come from the P4's internal adjustable LDO, which has to be set to 2.5 V before the DSI driver starts.
• Pixel clock. ESP-IDF notes that a higher pixel clock gives a higher refresh rate but may cause flickering if the DMA bandwidth is not enough. If the image tears or flickers, lower dpi_clock_freq_mhz first.

To copy bitmaps faster, the driver can use the 2D-DMA (esp_lcd_dpi_panel_enable_dma2d()).

Panels and touch

Espressif's ESP32-P4-Function-EV-Board pairs the P4 with a 7″ 1024×600 MIPI DSI capacitive touch screen through an LCD adapter board. M5Stack Tab5 units made before 14 October 2025 use an ILI9881C with a separate GT911 touch controller; later units use an ST7123 or ST7121 display-and-touch controller, and the init sequences are not interchangeable. Many capacitive panels use a GT911 touch controller, which answers at I2C address 0x5D or 0x14 depending on the INT level at reset.

Our MIPI DSI models include a 3.5″ 480×640, a 4.99″ 720×1280 IPS with ILI9881D and an 8″ 800×1280 IPS. Their lane configuration is confirmed per project: send us the board you use and we check 2-lane operation and the init sequence before samples.