MIPI DSI Displays
High-speed serial displays for Linux and Android SoCs: RK3568, i.MX8, Raspberry Pi and ESP32-P4.
3 matching display modules
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3.5" 480×640 TFT LCD, MIPI DSI (PJ3506G01-31H30P200C)
- Size
- 3.5"
- Resolution
- 480×640
- Brightness
- 200 nits
4.99" 720×1280 IPS TFT LCD, MIPI DSI (PJ5015B14-21H26P300)
- Size
- 4.99"
- Resolution
- 720×1280
- Brightness
- 300 nits
8" 800×1280 IPS TFT LCD, MIPI DSI (PJ8002I01-26H31P200)
- Size
- 8"
- Resolution
- 800×1280
- Brightness
- 200 nits
More standard models (8)
Full catalog →From our direct factories’ product tables. Datasheets and samples on request.
| Model | Size | Resolution | Interface | Brightness (cd/m²) | FPC pins | Viewing | Touch | Outline (mm) | |
|---|---|---|---|---|---|---|---|---|---|
| PJ3506G01-31H30P400 PengJi | 3.5″ | 480×640 | MIPI DSI | 400 | 30 | 6 o'clock | Optional | 67.3 × 96.2 × 4.0 | Request datasheet |
| PJ3401T01-25H39P350 PengJi | 3.5″ | 800×800 | MIPI DSI | 300-500 | 39 | All (IPS-type) | Optional | 96.6 × 99.0 × 2.35 | Request datasheet |
| PJ5015B04-21H50P600 PengJi | 5″ | 480×854 | MIPI DSI | 200-600 | 35 | 6 o'clock | Optional | 56 × 120.05 × 2.2 | Full specs → |
| PJ5014H01-17H25P450 PengJi | 5″ | 720×1280 | MIPI DSI | 400 | 25 | All (IPS-type) | — | 65.35 × 118.8 × 2.0 | Request datasheet |
| PJ5501X01-16H39P500 PengJi | 5.5″ | 1080×1920 | MIPI DSI | 600-1000 | 39 | All (IPS-type) | Optional | 64.3 × 118.2 × 1.55 | Request datasheet |
| PJ7010H01-26H30P300 PengJi | 6.98″ | 720×1280 | MIPI DSI | 200-500 | 30 | All (IPS-type) | Optional | 91.5 × 165.91 × 2.6 | Request datasheet |
| PJ7014H01-24H30P400 PengJi | 7″ | 1280×800 | MIPI DSI | 200-600 | 30 | All (IPS-type) | Optional | 161.2 × 105.5 × 2.4 | Request datasheet |
| PJ10109I02-25H40P200 PengJi | 10.1″ | 800×1280 | MIPI DSI | 200 | 40 | All (IPS-type) | — | 143 × 228.6 × 2.5 | Request datasheet |
How MIPI DSI works
MIPI DSI sends pixels over one clock lane and one to four differential data lanes using the D-PHY physical layer. Each lane commonly runs 500 Mbps–1.5 Gbps, so a 4-lane link carries 1920×1200 at 60 Hz with very few pins.
Panels operate in one of two modes:
- Video mode: the host streams pixels continuously, like RGB. This is used by most TFT panels from 5″ to 10.1″.
- Command mode: the panel has its own frame memory and the host only sends updates. This is common on small AMOLEDs and saves power.
Lane count and bandwidth
Resolution @60 Hz | Raw bandwidth (24-bit) | Minimum lanes |
|---|---|---|
720×1280 | ~1.3 Gbps | 2 |
1024×600 | ~0.9 Gbps | 2 |
1280×800 | ~1.5 Gbps | 2–4 |
1920×1200 | ~3.3 Gbps | 4 |
Real links need around 20% headroom for blanking and protocol overhead.
Bring-up checklist
- Match the lane count and lane order in the device tree.
- Load the panel init sequence (DCS commands) from the panel supplier. This is the step most often missing.
- Set timing (porches, sync widths, pixel clock) from the datasheet.
- Check reset and power sequencing: VCI/IOVCC, then reset, then init.
- Keep DSI traces short and impedance-controlled (100 Ω differential).
Platform notes: RK3568 and Raspberry Pi 5. Interface comparison: MIPI DSI vs LVDS vs eDP.
Frequently asked questions
Why does my MIPI DSI display stay black?
The most common causes are a missing or wrong panel init sequence, a lane-count mismatch, and wrong reset or power sequencing. Confirm the init table from the panel supplier first, then verify the DSI clock with a scope.
Can a microcontroller drive a MIPI DSI display?
Only MCUs with a DSI host, such as STM32F469/H747 or ESP32-P4. Most MCUs, including ESP32-S3, have no DSI, so use RGB or SPI panels or a bridge chip.
How long can a MIPI DSI cable be?
Keep it short, typically under 10–15 cm of FPC. For longer runs inside an enclosure, LVDS is more robust.
Not sure which display fits your design?
Send us your size, interface and host processor. A display engineer replies within 12 hours with 2–3 options, datasheets and init code. Samples from 1 pc.